The radiator of this cooling system covers both the graphprocessor and all
eight memory chips, though rubber pads are involved in the latter case. There
are two power field-effect transistors (FETs) and one stabiliser chip cooled
with help of this radiator. Of course, rubber pads have been used for them too.
The radiator consists of two parts attached loosely to each other. The
smaller is made of copper and serves for graphprocessor cooling while the
larger aluminium one is supposed to service those memory and power chips.
By the way, the copper part is well polished while the aluminium part doesn't
seem to have experienced any improvements after casting. There are 32 aluminium
ribs of variable length (from 32 mm to 118 mm and ˜0.3 mm
thick each) which are soldered to the copper plate (˜1.3 mm thick).
You can notice a rectangular hole in the aluminium part which is for Rage
Theater cooling. Oh yes, it's supposed to be for this purpose, but the chip
itself is missing. As a result, no video input capabilities. A fast 65 mm
fan with 33 wings by ADDA (AD6512HB-TB3 0.40A 12V) is mounted on the aluminium
part of the radiator and requires a regular 3-pin connector to draw power from.
Air is blown along the radiator's ribs in the left direction, and that's strange
a bit because there is no easy way for it to get outside of computer case. In
general, this is a pretty much unusual design, though not much effective
probably. All right, we'll see.
As it has been mentioned previously, the card is based upon an ATI RV570
graphprocessor which is clocked at 580.50MHz. It comprises a whole lot of
330 mln. transistors and is manufactured using a 80 nm technological
process by TSMC. This graphprocessor is somewhat simplified R580 which consists
of 384 mln. transistors and is manufactured using a 90 nm
technological process. It needs to mention that R580 is used for top performance
ATI/AMD video cards such as X1900XTX/X1950XTX and X1900XT/X1950XT. The primary
difference between R580 and RV570 is a reduced by 1/4 number of pixel and
texture pipelines: 36 pixel and 12 texture (12 pixel and 4 texture per cluster
subdivided for execution sets of 3 pixel and 1 texture pipeline each). The
number of vertex pipelines remains unchanged if compared to R580 and there are 8
of them. Although the architecture of ATI pixel and vertex shader hardware
hasn't changed from R300 to R580 with RV570 (until R600 which is of a totally
different architecture featuring unified shader pipelines), let's make a brief
review once again.
Every pixel pipeline consists of 3 execution units: a 32-bit floating-point
scalar unit, a 96-bit vector unit called Vec3 (processes three 32-bit
floating-point operands at once) and a branch execution unit for flow control
code. Both scalar and vector units are 2-stage pipelined: the first stage
(preparating) is for ADD instructions only while the second (primary) is for
ADD\MUL\MADD instructions with texture access. One pixel pipeline processes one
pixel per clock with up to either two 32-bit scalar operands or one 32-bit scalar
+ one 96-bit vector operand or just one 128-bit vector operand (considering a
32-bit scalar unit as an extension of a respective 96-bit vector unit). A vertex
pipeline architecture is different somewhat and comes in a fashion of one 32-bit
floating-point scalar unit + one 128-bit vector unit called Vec4 which processes
four 32-bit floating-point operands at once. In addition, a texture pipeline
consists of one addressing and one filtering unit as well as of a raster
operator (ROP) to handle rasterising, blending, anti-aliasing and depth or
stencil buffer related tasks.
In general, all 12 pixel pipelines of a single cluster are supposed to
render consequently 4 batches of 12 pixels given the same shader code (12x4
mode). The pixel and vertex processing logic of RV570 complies with the Shader
Model 3.0 (SM 3.0) specification even though there is no support for vertex
texturing implemented as there in none in R580 though. There are no locked
pipelines because cores with some defects are used for Radeon X1650XT cards
under the name of RV560 with one cluster disabled (i.e. minus 12 pixel and 4
texture pipelines), and a 128-bit data bus to video memory is involved instead
of a 256-bit one.
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There is a PCIe to AGP bridge called RIALTO. This chip has been observed for
the first time in AGP based video cards of Radeon X800 series, but seems to be
useful still. It complies with the AGP 3.0 specification, hence supports
data transfers at 8x of nominal bus speed with SBA (SideBand Addressing) and FW
(Fast Write), thus delivering up to 2.1GB/s of bandwidth or even more with the
AGP bus overclocking.
There are eight 512Mbit Hynix GDDR3 SDRAM 1.4ns (HY5RS123235 FP-14 —
PDF datasheet, 816Kb) memory chips, and each one
contains 8 banks x 2097152 32-bit words. So, there are 512Mb of video memory
with a 256-bit data bus (eight 32-bit channels actually) just like in Radeon
X1950XTX or X1950XT. These memory chips are clocked at 351.00MHz (1404.00MHz
effective) what corresponds to their marking — 350MHz (1400MHz
effective). Not a good news to overclockers probably.
It needs to mention that memory controllers of R520, R580 and RV570 are
different significantly to those implemented in earlier designs. There is no
cross-bar switch driving two or four memory channels but two identical 256-bit
wide rings which transfer data in opposite directions. Both rings have four bus
arbiters with hardware logic to drive two 32-bit channels. Effective data
transfer path between two particular arbiters is between 1/4 to 1/2 of the ring
length.
The graphprocessor stabiliser is based upon a Volterra 1165MF PWM controller
(VT1165MF) which drives two channels, and every of them features a Volterra
1165SF (VT1165SF) power FET. In addition, there is a Volterra 223TF (VT223TF)
chip to be held responsible for video memory power supply. Unfortunately, it's a
bit problematical to be more descriptive here because there are no data sheets
available on the Net. In theory, they may be obtained from Volterra directly
after signing a NDA (Non-Disclosure Agreement), but that's strange very much
because such agreements are supposed to protect intellectual property which has
very little to do with basic capabilities of stabilisers and FETs. It can be
stated only that this design runs VT1165SF FETs at clock speed of 1MHz, what
makes a problem even in case of solid electrolytic capacitors. That's right,
there are only two liquid electrolytic 100µF/16V capacitors of an unknown
brand installed. Of course, they can handle some secondary tasks only. The
primary load is imposed on 10µF multilayer ceramic capacitors (MLCCs)
which have been installed in large quantity: 30 units to feed the RV570 and 10
units to help the memory.
In general, it must be said that the card's quality isn't high enough to
correspond with the card's price. It seems like the manufacturer has been
inclined to save as much as possible on the components. All right, there is no
Rage Theater, not all capacitors have been installed, but why to save on a
piezoelectrical buzzer? It's missing together with all driving chips, though
their aggregate costs are miserable indeed. In addition, there are several
design flaws like the following one which has been fixed by some Sapphire
employee manually. For those unfamiliar with electronics, there is a conductor
on the left of the RIALTO where a transistor is supposed to be. Oh yes, one more
thing about this bridge chip: it gets very hot in run-time and deserves for some
radiator at least, not that funky pinky protective rubber pad which complicates
cooling even more, and that's why it has been removed.